Keynote Speeches

The Forwarding Plane: An Old New Frontier of Networking Research

Changhoon "Chang" Kim

Barefoot Networks

Abstract  - We all know how to program CPUs, making it easy to prototype new ideas, build new applications, and share them with others. Today it is commonplace to program not just CPUs, but almost any domain-specific processors, such as GPUs, DSPs, and even machine-learning accelerators (e.g., TPUs). Unfortunately networking has long been an exception to this trend; the network data plane -- packet processing -- has been dictated by fixed-function switching chips, which help up innovations in the fields of networking, computing, and storage all together. 

But this is changing quickly. The new PISA (Protocol-Independent Switch Architecture) ASICs promise multi Tb/s of packet processing with uncompromised programmability. P4, a new domain-specific high-level language designed for networking, additionally allows network engineers and developers to program PISA chips and other types of programmable packet-processing devices (e.g., FPGAs, NPUs, and S/W switches) in a declarative and intuitive fashion. PISA and P4 will entirely change the way people design, build, and run not just their networks, but their distributed systems and applications as well.

In this talk, I’ll first explain what PISA and P4 are, how they work, what kinds of design principles they are built on, and why they are made possible now. I’ll also introduce a few killer applications of these technologies. Then I’ll characterize PISA as a “relentless I/O-event execution machine” and show how this characterization opens up possibilities for joint-engineering a network and the distributed applications running on the network. I’ll conclude my talk by introducing a few such exciting examples.

Chang
About the speaker - Changhoon "Chang" Kim is a Director of System Architecture at Barefoot Networks and is also working actively for the P4 Language Consortium (P4.org). Before getting involved with P4.org and Barefoot, he worked at Windows Azure, Microsoft’s cloud-service division, and led engineering and research projects on the architecture, performance, and management of datacenter networks. Chang is interested in programmable networking technologies, network monitoring and diagnostics, network verification, self-configuring/running networks, and debugging and diagnosis of large-scale distributed systems. Many of his research contributions — including TPP, VL2, Seawall, EyeQ, Ananta, and SEATTLE — are adopted in large production systems. He received a few awards, including SIGCOMM 2017 Best Paper Award and Microsoft RockStar Award 2013.

 





The end of Moore's Law, the end of Networking
Gavin Stark
Netronome

Abstract  - The observation that the number of transistors on an integrated circuit doubles every two years - which was valid for many years - no longer holds true, for a variety of reasons. In addition the cost of staying close to this growth level has been increasing as well, impacting the benefit of large monolithic devices. In parallel with this silicon evolution the approaches to networking implementation (packetization, switching, routing, configuration) have changed throughout the years, and (particularly in recent times) the shape of the network has evolved, with data centre / cloud processing now being dominant. Yet, of course, the end goal of networking is fundamentally unchanged. This talk will look briefly at some of the reasons for the end of Moore’s law, from experience with building devices at 22nm and below, and some strategies to mitigate the effects; it will then use the basic end goals of networking, particularly within the data centre, to provoke thinking on how silicon can continue to evolve and improve systems' performance and efficiency.

About the speaker - Gavin Stark is the Chief Silicon Architect at Netronome and Visiting Industrial Fellow at the Department of Computer Science and Technology at Cambridge University. He has been designing high speed communications systems for over 20 years, with millions of network processors shipped; at Netronome he is now developing his seventh generation of network processing architecture. Prior to Netronome, Gavin held chief architect and CTO positions at Virata, Cirrus Logic and Basis Communications, which was acquired by Intel Corporation.  Gavin holds both an MA and a PhD from Cambridge University, England. His current interests range from open source hardware and hardware generation language design, to high performance heterogeneous computing, data visualisation and analysis. Gavin holds over eighty patents in areas including packet processing algorithms and network processor architecture, and has coauthored papers in computing and geoscience.